1. Field of the Invention
The invention relates to an alignment mark and alignment method using the same, and more particularly to marks and method for multi-layer alignment.
2. Description of the Related Art
Electronic elements, such as MOS or capacitors, are fabricated using integrated circuit fabrication comprising deposition, photolithography, etching, diffusion, and ion implantation.
In general photolithography, a photoresist layer is coated on a wafer, and the wafer is exposed in an exposure system, and then developed to transfer the pattern from the mask to the photoresist layer. Photolithography may be repeated several times to overlay multi-layer interconnect structures.
In the overlay step, inaccuracy of alignment must be controlled within an allowable range. For example, each exclusive mask used on a corresponding layer forms a predetermined pattern, in which a target formed in each mask enables alignment of a current layer with a previous layer.
Overlay error occurs easily during alignment and exposure because the mask on the wafer in the exposure system is not stable or temperature is not controlled.
FIGS. 1a to 1c are cross-sections of the conventional method for multi-layer alignment.
In FIG. 1a, a semiconductor substrate, such as wafer 10, is provided. A metal layer is formed on a chip of the wafer 10. A photoresist layer is formed on the metal layer. A first mask 11 having a pattern is exposed to form the pattern on the photoresist layer by a light source, and the photoresist layer is developed to form a pattern on the photoresist layer. The metal layer is etched to form a first metal wire layer 11a using the photoresist layer as a mask. The photoresist layer is removed. The first metal wire layer 11a matches the pattern of the first mask layer 11, wherein a pair of first marks 111 and 112 in the first metal wire layer 11a correspond to first marks 101 and 102 in the first mask layer 11.
FIG. 1b is a top view of multiple layers formed by the first mask, wherein the layers are the metal wire layers 11a. In FIG. 1b. first marks 101 and 102 are formed on the X and Y axes of the first mask layer 11 respectively. The first marks 101 and 102 align exactly with the alignment mark of the wafer to form the corresponding first marks 111 and 112 of the metal wire layer 11a. 
FIG. 1c is a cross section of the wafer with multiple layers formed by the first mask 11 where photolithography is performed.
FIG. 1d is a top view of the multiple layers formed by the second mask, comprising metal wire layers 11a. FIG. 1e is a top view of the pattern formed by the second mask on the pattern formed by the first mask. FIG. 1f is a cross section of the wafer with multiple layers formed by the second mask where photolithography is performed.
In FIG. 1d, the second mask is exposed after the first mask 11. Second marks 121 and 122 are formed on the X and Y axes of the second mask 12 respectively. The second marks 121 and 122 enable a second metal wire layer 12a to correspondingly form on the first metal wire layer 11a. 
After photolithography, the wafer is deformed by high temperature in oxidation or thermal process, and the alignment marks of the metal wire layer are also deformed. In FIG. 1g, the position of the first metal wire layer 11a varies from the second metal wire layer 12a because of the difference in the direction of deformation between the first metal wire layer 11a and the second metal wire layer 12a. 
In FIG. 1h, the third metal wire layer 13a is formed on the second metal wire layer 12a and corresponds to the first metal wire layer 11a. The third mask, forming the third metal wire layer 13a, cannot align with the first metal wire layer 11a with the second metal wire layer 12a because the position of the alignment mark has changed.
In FIG. 1i, the third metal wire layer 13a is formed on the second metal wire layer 12a and corresponds to the second metal wire layer 12a but not the first wire layer 11a. The pattern is not transferred well if layers are not aligned precisely before exposure of the photoresist layer, making the chip unusable.
In ULSI fabrication, electronic element size is reduced during various steps, such that the quality of resolution and overlay accuracy of the conventional exposure process is sufficient.